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Europe, Germany, Münchendorf

Posted 12 days ago

Senior FPGA Developer (SystemVerilog)

🏢 Terra Quantum

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Role Type

🛠️ Engineer / Developer

Role Focus

🏗️ Build Systems

Seniority

🌳 Senior / Lead

Employer Type

🏢 Industry

This Senior FPGA Developer role is critical for building the core Quantum Key Distribution system. The main responsibility is full ownership of the FPGA design, including architecture, implementation in SystemVerilog, and achieving timing closure for high-rate interfaces on AMD/Xilinx platforms. The developer must also collaborate closely with software and embedded teams to ensure reliable system integration and is expected to mentor junior engineers.

Key Responsibilities

Own the SystemVerilog RTL architecture and implementation for Artix-7 and Kintex UltraScale FPGAs used in the Quantum Key Distribution system.

Implement and integrate crucial hardware interfaces such as DDR3/DDR4 controllers, PCIe endpoints, and Ethernet/SFP paths, including evaluating and integrating third-party IP.

Manage XDC constraints, apply practical floorplanning, and ensure consistent timing closure across all operating corners.

Establish and maintain a professional verification environment using tools like ModelSim/Questa, self-checking testbenches, and Python/cocotb co-simulation.

Define clear register maps and interface contracts for system integration and collaborate closely with software and firmware teams.

Provide mentorship to a junior engineer and establish engineering discipline, style guides, and design documentation.

Required Skills

5+ years of experience in production FPGA development on AMD/Xilinx platforms.

Expertise in SystemVerilog RTL design.

Strong proficiency in XDC constraints, clock domain crossing (CDC) methodology, and achieving consistent timing closure.

Hands-on experience implementing high-speed interfaces like DDR3/DDR4, PCIe endpoints/DMA, and Ethernet/SFP.

Strong verification background using self-checking testbenches and proficiency with ModelSim/Questa simulation tools.

Experience with continuous integration (CI) for HDL, including scripted simulation, synthesis, and implementation using Tcl, Make, or Python.

Experience with system integration involving software/firmware (register maps, driver contracts, Hardware-in-the-Loop testing).

Nice-to-have Skills

Expertise in AXI4/AXI-Stream and DMA performance tuning.

Exposure to formal verification methods.

Scripting for automation (Python/Tcl) and experience with CI systems (GitHub Actions/Jenkins).

Familiarity with MicroBlaze/Zynq ecosystems and low-level firmware or C driver collaboration.

Proven delivery on Artix-7 and/or Kintex UltraScale using Vivado.

Technology Tags

QKD

The role is dedicated to building the core hardware for the Quantum Key Distribution system.

Quantum Comms

The job is centered on building a Quantum Key Distribution system, a core component of quantum communication networks.

FPGA controllers

The developer is responsible for end-to-end RTL ownership on AMD/Xilinx FPGAs using SystemVerilog and Vivado.

Classical programming

The role requires scripting proficiency in Tcl, Make, and Python for verification, simulation, synthesis, and CI automation.

Signal processing

The job involves defining and implementing high-speed datapaths and deterministic acquisition/timing/sifting layers, which require signal processing expertise.

System Networks

The role involves defining system integration requirements, interfaces like PCIe and Ethernet, and collaborating on driver contracts and throughput budgets with software and firmware teams.

Microelectronics

The job involves highly specialized implementation and interfacing using FPGA components, focusing heavily on constraints, timing closure, and floorplanning.

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