Cambridge, UK | Full-time | Fixed-term | £30,000 - £35,000 (pro rata) DOE
About Us
Riverlane's mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry's defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.
We recently raised $75 million to accelerate our cutting-edge R&D. We partner with many of the world's leading quantum computing companies and governments to accelerate their path to utility-scale quantum computers. We're making remarkable progress and growing fast. Join us!
About The Role
Riverlane's Local Clustering Decoder (LCD) is at the forefront of quantum error correction, capable of decoding surface code quantum memory experiments in under 1 microsecond per round of syndrome extraction - fast enough to keep up with today's fastest superconducting qubits.
Its architecture already supports a wide variety of logical qubit operations that will be essential for the fault-tolerant quantum computers of the near future. As an Engineering Intern, you will be responsible for investigating and implementing architectural optimisations that unlock greater flexibility and performance in the LCD decoder. Your work will help ensure this system meets the demands of next-generation quantum hardware, expected to come online within the next five years.
What You Will Do
- Collaborate with experienced hardware and software engineers to explore and evaluate architectural optimisations
- Enhance the decoder's architecture to improve both flexibility and processing speed
- Contribute to key design decisions involving space/time trade-offs to balance functionality with performance
Requirements
What we need
- Proficiency in Python
- Solid understanding of low-level computer architecture
- Willingness to learn about FPGA development, quantum computing, and quantum error correction
Even better if you have
- Familiarity with quantum computing or quantum error correction
- Understanding of optimisation concepts
- Exposure to networking principles
- Experience with RTL (Register Transfer Level) development for FPGA/ASIC
Important notes
- We are only able to accept applications from individuals who have the right to work in the UK (including those who hold a valid UK student visa). Please note, for PhD students, there is the requirement to temporarily step out of your PhD to complete the internship, which may impact your right to work status.
- You must be available full-time for 10 to 12 weeks over the summer vacation period, preferably starting on Monday 15th June 2026 until Friday 4th September 2026.
- We require a signed agreement from you assigning the ownership of any IP produced during your internship to Riverlane.
- Internships are based at our Head Office in Cambridge, UK.
How To Apply
Please upload a CV and covering letter here. Your CV should include the grades that you have so far received in your degree(s). The covering letter should explain why you are applying for the internship and what skills and experience you can bring to the role.
Our summer internships start on
Monday 15th June 2026 until Friday 4th September 2026.
Deadline
Please submit your application by
Sunday 16th November 2025. Interviews will be held in Cambridge (or virtually if required) during
late November/early December 2025.
Benefits
Stipend
Interns receive a competitive stipend. The annual stipend is £30,000 for Bachelor's, £32,000 Master's students and £35,000 for PhD students (pro rata). We will also pay for any expenses incurred as part of your role e.g. travel to meetings or conferences etc. Regrettably, we are unable to pay for travel to Cambridge or accommodation in Cambridge. Please note that we are unable to pay for travel to Cambridge or accommodation in Cambridge.
What Can You Expect From Us
Alongside a competitive salary, you can expect a diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities.
We also offer a regular programme of learning events, as well as complimentary snacks and refreshments and regular social and cultural events, including yoga, paddle, movie nights and more.
If you have any queries, please contact jobs@riverlane.com.
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.
Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don't meet every single qualification. We'd love to hear from you.
If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.