qubitsok.com
Cut Noise. Work Quantum.
Europe, United Kingdom, Oxford
•
Posted 231 days ago
🏢 Oxford Ionics
Role Type
Role Focus
Seniority
Employer Type
This QPU Design Engineer role is central to bringing ion-trap chip designs into production for Oxford Ionics' quantum computing systems. The engineer will be responsible for the layout of complex electrode structures on custom QPU ICs and associated PCBs. This position involves working closely with scientists and fabrication teams to ensure designs are manufacturable and compatible with wider system constraints.
Key Responsibilities
Create the layout of QPU ICs, including multi-layer metal track routing as well as modification of the ion trap layouts and scripting.
Partner with ion-trap scientists to shape and refine trap and array designs, ensuring alignment with experimental goals and physical constraints.
Design surrounding system hardware, such as silicon and ceramic interposers, as well as carrier PCBs.
Design QPU components with full consideration of system-level constraints, including vacuum chamber integration, cryogenics, and thermal management.
Specify, source, and document components while working closely with manufacturing teams to ensure smooth QPU build and test processes.
Required Skills
Hands-on experience in IC layout (approximately 5 years)
Hands-on experience in PCB design and layout (approximately 5 years)
Self-motivation
Solutions-focused approach
Ability to collaborate effectively across multidisciplinary teams
Strong communication skills
Solid foundation in science or engineering
Nice-to-have Skills
Exposure to photonic design
Exposure to RF design
Relevant academic qualifications or equivalent industrial experience
Background in commercial or industrial environments
Technology Tags
The job explicitly states the company uses "unique trapped-ion technology" and the engineer will work on "ion-trap chip designs" and with "ion-trap scientists."
The role is centered on "Printed Circuit Board (PCB) designer or Integrated Circuit (IC) layout engineer" and "QPU ICs," which are core microelectronics tasks.
Key responsibilities include "Designing QPU layouts" and creating "layout of complex electrode structures," which directly constitute circuit design at the quantum level.
The engineer is responsible for "integrating components such as integrated photonics" and ideally has "exposure to photonic and RF design."
The job description specifically lists "RF design" as a desired area of experience for the QPU Design Engineer.
The engineer must design QPU components with "full consideration of system-level constraints, including vacuum chamber integration" and "cryogenics."
A central task is "integrating components such as integrated photonics" onto the custom QPU ICs.