Senior Quantum Engineer

Overview

Microsoft's mission is to empower every person and every organization on the planet to achieve more. At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology.  

We are looking for a diverse set of talented and focused people to accelerate the delivery of useful quantum computers. Microsoft has an internal program pursuing topological qubits for large-scale quantum computing. We are also working closely with a growing list of companies to advance quantum computer systems at every layer of the stack and bring them to market on the Microsoft Quantum accelerator platform. We believe AI can accelerate both the creation of useful quantum computers and bring-in the timelines for their realization. For more information about the Microsoft Quantum team, please visit  https://quantum.microsoft.com/   

The Quantum Design team at Microsoft is seeking a Senior Quantum Engineer to design and simulate the performance of next-generation qubit chips. This role offers a unique opportunity to shape revolutionary technology and accelerate progress toward scalable quantum computing based on topological qubits. 

As a Senior Quantum Engineer, you will take a key role in designing Quantum Processor Unit (QPU) chips, including wiring, layout, and interfaces, ensuring seamless integration with control and readout layers. You will collaborate closely with experts in systems design, fabrication, packaging, and control in an environment that values innovation, adaptability, and interdisciplinary expertise.

Qualifications

Required/Minimum Qualifications

• Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
• • OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
  • OR Doctorate in Physics, Engineering, or related field AND 1+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR equivalent experience.
• Familiarity with industry-standard or custom developed chip and circuit design/layout tools.
• Familiarity with RF integrated-circuit simulation tools, e.g. Ansys, Sigrity, Comsol.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
• Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through both hardware and software development.
• Ability to design and build AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval (e.g. instrument manuals, design docs).

Additional or Preferred Qualifications

• 3+ years of industry experience in chip or circuit board design and layout like mixed-signal integrated circuits, high-speed RF/digital circuits or equivalent experience.
• Experience with integrated circuit (IC) or application specific IC design, physical design, physical verification, register transfer level (RTL) to graphic data system (GDS) flow.
• Experience with industry-standard integrated circuit design tools, e.g. Cadence, Altium, and RF, mixed-signal and integrated-circuit simulation tools, e.g. Ansys, Sigrity, Comsol.
• Experience with industrial semiconductor device design and fabrication processes and tools like process design kits and electronic design automation.
• Experience with coding in programming languages such as Python and collaborative code development environments (e.g., Git, GitHub).
• Knowledge of quantum computing principles and hands-on experience with quantum computing hardware, such as superconducting qubits or spin qubits.

Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until November 7, 2025.

#Quantum #QuantumCareers #MDQCareers

Responsibilities

• Design & Layout: Develop Quantum Processing Unit (QPU) chip designs and interfaces to readout/control layers using simulation-driven, fabrication-aware workflows. 

• Radio Frequency (RF) Simulation: Perform RF simulations of QPU chips and interface layers to define design requirements and optimize control/readout performance. 

• Cross-Team Collaboration: Partner with fabrication, systems, packaging, and control teams to co-design QPUs, incorporating constraints and requirements. 

• Tool Development: Build and maintain design tools, functionalize devices into models, and enable co-design with internal teams and external partners. 

• Process Optimization: Apply integrated circuit design principles and engineering best practices to improve design processes and recommend optimizations. 

Other: 

• Embody our Culture and Values