qubitsok.com
Cut Noise. Work Quantum.
Remote
•
Posted 14 days ago
🏢 IonQ
•
USD 110K - 144K per year
Role Type
Role Focus
Seniority
Employer Type
Visa / Relocation Details
The Senior Mask Layout Engineer will join the Fab Tapeout and Validation Team, taking ownership of full-reticle tapeouts for photonic and electronic components used in trapped-ion quantum computers. This role involves developing and maintaining internal Process Design Kits (PDKs) and automated circuit layout libraries, often utilizing Python scripting. The engineer must collaborate closely with design and testing teams to advance new quantum technology for scalable computing, memory, and networking solutions.
Key Responsibilities
Conduct Python-based layout for full-reticle tapeouts with commercial foundries.
Develop and maintain internal component PCell and automated circuit layout libraries.
Interface with designers, test engineers, packaging engineers, and the foundry team to define layout rules and component designs.
Implement physical verification checks of layouts, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS).
Develop detailed documentation of tapeouts and lead layout reviews with other team members.
Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows.
Required Skills
Bachelor's degree in Photonics, Physics, Electrical Engineering, or a related field, or equivalent practical experience.
Knowledge of semiconductor manufacturing processes and techniques.
Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation.
2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout.
Nice-to-have Skills
M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or a related field.
5+ years experience generating layout files for complex semiconductor flows with custom elements, such as integrated photonics or superconducting circuits.
Past ownership of full-reticle tapeouts with commercial foundries.
Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys.
Proficiency in physical verification including DRC, LVS, and Electrical Rule Checking (ERC).
Excellent verbal and written communication skills.
Ability to work independently, prioritize tasks, and manage time effectively in a deadline-oriented environment.
Technology Tags
The engineer focuses on tapeouts for components used specifically in trapped-ion quantum computers.
The job requires experience with layout files and workflows for integrated photonics.
Required knowledge includes semiconductor manufacturing processes and techniques for mask layout.
The mask layout engineering role deals directly with physical design at the micro and nano scale for fabrication.
Responsibilities include conducting Python-based layout for tapeouts and writing automation scripts.
Desirable experience includes generating layouts for complex semiconductor flows involving superconducting circuits.
The role involves creating layouts for integrated photonic and analog electronic layers on a chip.
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